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If a program, logic NOT operation is performed on one byte. The result is a byte with inverted
bits. If byte is considered to be a number, the inverted value is actually a complement of that
number, i.e. the complement of a number is what is needed to add to it to make it reach the
maximal 8 bit value (255).
EXCLUSIVE OR Gate
The EXCLUSIVE OR (XOR) gate is a bit complicated comparing to other gates. It represents a combination of all
the previously described gates. A logic one (1) appears on its output only when the inputs have different logic
states.
In a program, this operation is commonly used to compare two bytes. Subtraction may be
used for the same purpose (if the result is 0, bytes are equal). The advantage of this logic
operation is that there is no danger to subtract larger number from smaller one.
Register
A register or a memory cell is an electronic circuit which can memorize the state of one byte.
http://www.mikroe.com/en/books/picmcubook/ch0/ (11 of 30)5/3/2009 11:28:39 AM
- BASIC CONCEPT 3
- Fig. 0-8 High and Low nibbles 9
- Fig. 0-17 Register 12
- Fig. 0-27 Timers/Counters 21
- Fig. 0-28 Timer Operation 22
- Fig. 0-31 Watchdog Timer 25
- Internal Architecture 26
- How to make the right choice 28
- ● AN3 Third analog input 34
- Table 1-1 Pin Assignment 35
- Fig. 1-4 CPU Memory 37
- Fig. 1-5 ROM Memory Consept 38
- Table 1-2 Address Banks 40
- Table 1-3 SFR Bank 0 41
- Table 1-4 SFR Bank 1 42
- Table 1-5 SFR Bank 2 43
- Table 1-6 SFR Bank 3 43
- Fig.1-7 Interrupt System 44
- Chapter 2: Core SFRs 45
- Table 2-1 46
- Table 2-2 48
- Fig. 2-9 Interrupt SFRs 49
- Fig. 2-10 INTCON Register 49
- Fig. 2-11 PIE1 register 50
- Fig. 2-12 PIE2 Register 51
- Fig. 2-13 PIR1 Register 52
- Fig. 2-14 PIR2 register 53
- Fig. 2-15 PCON register 54
- Fig. 2-17 PCLATH Registers 55
- Chapter 3: I/O Ports 57
- Port A and TRISA Register 58
- Fig. 3-3 ULPWU Unit 59
- Fig. 3-4 Sleep Mode 60
- Fig. 3-6 WPUB register 61
- Fig. 3-7 Pull-up resistors 61
- Fig. 3-8 IOCB register 62
- Fig. 3-9 Keyboard Example 62
- Fig. 3-10 ICSP Connection 63
- Chapter 4: Timers 67
- Fig. 4-1 Timer TMR0 68
- Fig. 4-2 OPTION_REG Register 68
- Fig. 4-5 Timer TMR1 71
- Fig. 4-8 TMR1 in timer mode 73
- Fig. 4-11 Counter Mode 75
- Fig. 4-12 T1CON Register 75
- Fig. 4-13 Timer TMR2 77
- Fig. 4-14 T2CON Register 77
- Chapter 5: CCP Modules 79
- Fig. 5-1 CCP1 Module 80
- Fig. 5-2 CCP1 in Capture mode 80
- Fig. 5-3 CCP1 in Compare mode 81
- Fig. 5-4 CCP1 in PWM mode 82
- Fig. 5-6 PWM module 83
- Fig.5-7 PWM Mode 83
- Fig. 5-8 CCP1CON Register 85
- Table 5-4 CCP1CON Register 85
- Table 5-5 Modes of Operations 86
- Fig. 5-9 CCP2 Module 86
- Fig. 5-10 CCP2CON Register 87
- Table 5-6 CCP2CON Register 87
- Fig. 5-12 Half-Bridge Mode 89
- Fig. 5-13 Half Bridge Mode 89
- Fig. 5-15 Full-Bridge Mode 90
- Fig. 5-16 Forward Mode 91
- Fig. 5-17 Reverse Mode 91
- Fig. 5-18 PWM1CON Register 92
- Fig. 5-19 ECCPAS Register 92
- EUSART Asynchronous Mode 95
- Fig. 6-5 Receiving 9-bit Data 98
- Fig. 6-7 Sending Data 99
- Fig.6-8 TXSTA Register 99
- Fig.6-9 RCSTA Register 100
- BAUDCTL Register 104
- Fig. 6-11 BAUDCTL Register 105
- SPI Mode 107
- Fig. 6-13 SPI Mode 108
- Fig. 6-14 SPI Mode 108
- I²C mode 109
- Fig. 6-21 Data Transfer 111
- Fig. 6-23 SSPSTAT Register 112
- Fig. 6-24 SSPCON Register 114
- Fig. 6-25 SSPCON2 Register 115
- Fig. 6-27 I²C in Master Mode 116
- I²C Master Mode 117
- Useful notes 119
- Chapter 7: Analog Modules 121
- A/D Acquisition Requirements 123
- How to Use A/D Converter? 123
- Fig. 7-6 Analog Comparator 127
- Fig. 7-7 VREF 128
- Fig. 7-8 CM1CON0 Regsiter 129
- Fig. 7-13 VRCON Register 133
- External Clock Modes 137
- Fig.8-3 PICflash Program 138
- Fig. 8-4 External Oscillator 138
- Internal Clock Modes 140
- Internal Oscillator Settings 141
- Two-Speed Clock Start-up Mode 142
- Fail-Safe Clock Monitor 143
- Fig.8-18 EECON1 Register 146
- Fig. 8-22 Noises 149
- Fig. 8-23 Master Clear Pin 149
- Chapter 9: Instruction Set 150
- Data Transfer Instructions 152
- Arithmetic-logic Instructions 152
- Bit-oriented Instructions 152
- ADDLW - Add literal and W 154
- ADDWF - Add W and f 154
- ANDLW - AND literal with W 155
- ANDWF - AND W with f 156
- BCF - Bit Clear f 157
- BSF - Bit set f 158
- CALL - Calls Subroutine 161
- CLRF - Clear f 161
- CLRW - Clear W 162
- CLRWDT - Clear Watchdog Timer 163
- COMF - Complement f 163
- DECF - Decrement f 164
- GOTO - Unconditional Branch 166
- INCF - Increment f 167
- IORWF - Inclusive OR W with f 169
- MOVF - Move f 170
- MOVLW - Move literal to W 171
- MOVWF - Move W to f 172
- NOP - No Operation 173
- Fig. 9-1 f Register 176
- Fig. 9-2 f Register 177
- SLEEP - Enter Sleep mode 178
- SUBWF - Subtract W from f 179
- SWAPF - Swap Nibbles in f 180
- XORWF - Exclusive OR W with f 181
- ELEMENTS OF ASSEMBLY LANGUAGE 185
- MACROS AND SUBROUTINES 191
- WRITING A NEW PROGRAM 200
- Appendix B: Examples 206
- ADDITIONAL COMPONENTS 209
- EXAMPLE 1 224
- EXAMPLE 2 227
- EXAMPLE 3 228
- Example 4 229
- Example 5 231
- EXAMPLE 6 233
- EXAMPLE 7 235
- EXAMPLE 8 237
- EXAMPLE 9 239
- EXAMPLE 10 240
- EXAMPLE 11 242
- EXAMPLE 12 244
- EXAMPLE 13 246
- goto Lsdon 247
- EXAMPLE 14 249
- EXAMPLE 15 252
- EXAMPLE 16 256
- COMPILING PROGRAM 261
- PROGRAMMING A MICROCONTROLLER 262
- Development systems 265
- Development system EasyPIC5 266
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